Although they can in principle be applied to any desired integrated circuits, the present invention and the problem on which it is based are explained with reference to integrated circuits produced using silicon technology.
Metallizations in contact holes of semiconductor circuits for connecting metal planes or metal and semiconductor planes which lie above one another, for example in DRAM and logic circuits, contain multiple metal layers comprising low-resistance bonding and diffusion barrier layers and fillings comprising nucleation and bulk layers.
PVD (Physical Vapor Deposition) processes and MCVD (Metal Chemical Vapor Deposition) processes are used to produce layers of this type.
A typical 4-layer system for a contact-hole metallization is:Ti(PVD)+TiN(PVD)+W nucleation (MCVD)+W bulk (MCVD)
The need to match the individual layers to one another and the use of different deposition processes result in complex development work and disruption to the production sequences caused by deviations in the individual layer uniformity and increased levels of defects.
For smaller structures with higher aspect ratios (quotient of height and diameter), complete filling can no longer be achieved. In this case, unfilled voids remain in the center of the contacts and act as a contamination source for example for a following metal plane. Further reductions in the minimum feature size in microelectronics mean that the absolute diameter of contact holes both on the silicon substrate and between the metal planes is being constantly reduced further, while at the same time the aspect ratio is rising.
For future technology generations, the present invention will provide a reliable contact between a metal plane and silicon or between different metal planes and, with simultaneous simplification of the process flow, will make it possible to considerably reduce the process costs.
Hitherto, to ensure a reliable contact, for example on a silicon substrate, first of all a liner layer of titanium or titanium nitride has been deposited. This liner layer is then heat-treated in a forming-gas atmosphere at approx. 600° C. This step leads to one-off conversion of some or all of the titanium into titanium silicide in order to reduce the contact resistance. Furthermore, the formation of TiN or the increase in the thickness of the titanium nitride which is already present improves the barrier layer in order to avoid subsequent fluorine attack on silicon. The Ti/TiN layers may, for example, be applied by sputtering.
Nowadays, in some cases expensive MOCVD TiN processes or CVD Ti/TiN processes are already being used. By way of example, selective CVD-Ti (precursor TiCl4, TiBr or TiI) is used so that it is deposited only at the bottom of the contact hole. The deposition takes place at high temperatures of over 500° C., so that TiSi forms immediately. This is followed by the CVD TiN deposition, which is likewise carried out at temperatures of over 500° C. and fills the contact hole (same Ti-containing precursor+nitrogen-containing gas). One drawback of this method consists in the fact that the formation of silicide during the CVD-Ti deposition is very difficult to control, with the result that the contact resistances have a greater scatter.
What are known as ultra-shallow junctions can no longer be produced in this way. In addition, the CVD Ti process is very expensive. In the known process, after the liner has been deposited, tungsten is deposited by means of CVD (precursor WF6). This deposition once again comprises two steps, namely a first step, in which a nucleation layer is deposited, and a second step, which represents the actual bulk layer deposition.
Finally, a two-stage CMP (CMP=Chemical Mechanical Polishing) process is used to remove firstly the excess tungsten and then the barrier comprising Ti/TiN on the top side of the wafer. To further reduce costs, in particular the DRAM process has combined the filling of contact holes with the production of a first metal wiring in the form of a dual damascene process. However, tungsten has a very high bulk resistance, which leads to power losses in the corresponding circuits.
By optimizing the layer thicknesses, temperatures, pressures, deposition powers and gas compositions, it has been possible to use the abovementioned multilayer systems Ti/TiN/W (nucleation)/W (bulk) in semiconductor circuits for technologies as advanced as 170 nm. However, technologies of smaller than 140 nm require simplified process sequences and optimized layer systems.
Hitherto, a particular problem has been that of planarizing the titanium by means of the CMP process after it has been deposited, specifically in conjunction with tungsten, since, as has been stated, in a two-stage process first of all the tungsten has to be polished with chemical assistance, and then the Ti/TiN has to be polished predominantly by mechanical means.